#Instruction Level Parallelism
#Approaches to Exploit Parallelism
#Hardware-Based Techniques
- Pipeline: Executes different stages of the execution process in parallel.
- Branch Prediction and Speculation: CPU performs tasks that might not be needed to optimize execution flow.
- Dynamic Scheduling: Rearranges instruction execution to reduce stalls.
#Software-Based Techniques
- Loop Unrolling: Substitutes loops with repetitions to utilize instruction and data-level parallelism.
- Others: Additional compiler optimizations to find parallelism at compile time.
#Data Level Parallelism
Three variations of SIMD
- Vector architectures
- Multimedia SIMD instruction set extensions
- Graphics processing units (GPU)
#Thread Level Parallelism
#Simultaneous Multithreading (SMT)
#Multi-processing
Microprocessor